Tetra Semiconductors’ Sample of the New PAM4 200/400G Ethernet Transceiver Chipset Now Available

Zurich, March 5, 2020

Tetra Semiconductors Ltd., Zurich, Switzerland announces their new TS2 Transceiver Chipset for 200G/400G Ethernet SR/LR applications is now available. The chipset combines outstanding performance with minimal power consumption and offers the cost-effectiveness required to build competitive 200G/400G optical modules.

Tetra Semiconductors’ transeiver chipset includes 4 Channel PAM4 VCSEL Drivers and 4 Channel PAM4 TIAs as well as 4 Channel PAM4 CDR chips, all running in the range of 23-29 Gbaud suitable for 200G and 400G Ethernet/Infiniband and other proprietary solutions. The transceiver chipset enables QSFP-DD/OSFP module designs with best in class power consumption of <7 W for the complete 400G module. The TS2 chips are based on Tetra’s 3rd generation patented analog CDR allowing for very low power due an extremely simple, scalable PAM4 decoding scheme. Tetra was the first to show a DSP-free 56 Gbaud link using their unique PAM4 CDR technology! (

26Gbaud output eye diagram of the TSR2PAM operating in combination with a high speed photodiode from Albis Optoelectronics

Circuit optimization and newly designed optical front-ends allow for the integration of the CDR with the optical front-ends onto a single chip resulting in the best possible power and a compact size. All chips include adaptive equalization including CTLE and DFE as well as pre- and post-cursor equalization to recover/preshape for the losses of the in/output signals. 

26Gbaud VCSEL optical Eye diagram of the TST2PAM

Features included in the chips are:

  • 4 Channel PAM4 CDR with integrated VCSEL Driver
  • 50 Ohm inputs with adaptive CTLE and DFE equalization
  • PAM4 VCSEL Driver with individual eye adjustment to overcome possible VCSEL nonlinearities
  • Power consumption of 390 mW/Channel (10 mA Average Current; 10 mA Modulation Current)
  • Size: 2mm x 1.5mm
  • 4 Channel PAM4 CDR with integrated TIA
  • PAM4 TIA with gain controlled linear amplifier that includes adaptive CTLE and DFE equalization
  • 50 Ohm outputs with pre- and postcursor equalization
  • Power consumption of 430 mW/Channel (300 mVpp output swing)
  • Size: 2mm x 1.5mm
  • 4 Channel PAM4 CDR with high output swing of up to 1.4Vpp, enough to drive silicon photonics modulators
  • 50 Ohm inputs with adaptive CTLE and DFE equalization
  • 50 Ohm outputs with pre- and postcursor equalization
  • Power consumption of 410 mW/Channel (@ 1 Vpp output swing)
  • Size: 1.8mm x 1.5mm

Samples of all three chips are  available now.

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